InAs Quantum - Well MOSFET ( L g = 100 nm ) for Logic and Microwave Applications

We report a recessed quantum-well (QW) InAs MOSFET with enhancement-mode operation down to 100 nm gate lengths. The device features a composite insulator consisting of an MBE-grown 2 nm InP barrier plus an ex-situ ALD-deposited 3 nm Al2O3 for an estimated EOT of 2 nm. Our devices exhibit excellent short-channel effects down to the Lg = 100 nm regime. InAs QW MOSFETs exhibit record transconductance gm = 1.73 mS/μm and high-frequency performance (fT = 245 GHz and fmax = 355 GHz). These are the highest values of fT and fmax for any III-V MOSFET. Introduction: III-V semiconductors have emerged as a promising channel material for future CMOS low power logic applications [1-2]. Their enhanced electron transport properties offer significant power reduction through aggressive supply power (VDD) scaling. To maximize VDD scaling for logic applications both transconductance (gm,ext) and subthreshold slope (S) must be optimized. We report three significant advances towards these goals: first an InAs sub-channel to improve carrier transport, second an optimized gate stack process with thin EOT and low Dit to improve S, and third an improved layer structure with thin InP barrier (to reduce access resistance and surface depletion) and optimized Si δ-doping (to improve S and reduce RSD). Experimental: Fig. 1 and Fig. 2 show a cross section of the device structure and a corresponding TEM image of an Lg = 100 nm device, respectively. From top to bottom, the epitaxial layer structure consists of a heavily doped cap (20 nm In0.7Ga0.3As) layer, 2-nm InP barrier, 10-nm In0.53Ga0.47As/InAs/In0.53Ga0.47As composite channel, 5 nm In0.52Al0.48As spacer, Si δ-doping, and 300-nm In0.52Al0.48As buffer on InP substrate. The thin 2 nm InP barrier was introduced to reduce access resistance and improve charge control, EOT and immunity to short channel effects as well as to improve Dit [3]. The device also features a 5 nm thick InAs sub-channel to improve carrier transport and electron confinement in the channel. In a calibration sample, we measured μe,Hall = 11,200 cm/V-sec and ns,ch = 9 x 10/cm at 300 K. Inverted Si δ-doping was used to supply carriers to the S/D access region and reduce RSD. It is critical to carefully select the inverted Si δ-doping density to achieve the best trade-off of threshold voltage (VT), subthreshold slope (S) and parasitics resistance (RSD) [4]. Fig. 3 shows channel carrier density as a function of gate potential for various Si δ-doping densities. The ability to modulate the channel carriers get worse as Si δ-doping increases, indicating that Si δ-doping needs to be carefully optimized, for acceptable subthreshold characteristics. In this work, we have chosen a value of 1 x 10/cm, as the Si δ-doping, which resulted in both low RSD and excellent electrostatic control. Fig. 4 shows the corresponding conduction band profile with Si δ-doping = 1 x 10/cm at VGS = 0 V. Device fabrication was similar to that of a conventional HEMT [5], except for the deposition of a gate oxide prior to metal gate formation. After S/D ohmic contact with a 2 μm spacing, a gate pattern using single-layer ZEP-520A was defined by e-beam lithography. This was transferred to a passivating SiO2 layer by CF4 plasma. Subsequently, the cap was etched using a diluted citric acid based solution. After removing the e-beam resist, 3 nm of Al2O3 was deposited by ALD and the Pd/Au metal gate was evaporated. In this way, devices with Lg from 100 nm to 250 nm were fabricated. Results and Discussion: Fig. 5 shows the device output characteristics demonstrating excellent pinch off and low RSD (323 Ohm-μm). Fig. 6 shows typical subthreshold characteristics with Lg from 100 nm to 250 nm. These devices show excellent subthreshold behavior and ION/IOFF ratio (~10) down to Lg = 100 nm. The gate leakage (Ig) is lower than 0.1 nA/μm at all measured bias conditions. InAs QW MOSFET with Lg = 100 nm exhibits VT = +0.2 mV (defined as ID = 1μA/μm) and subthreshold swing (S) = 105 mV/dec at VDS = 0.5 V. This results in an IOFF = 5 X 10 A/μm at VGS = 0 V and VDS = 0.5 V. The attainment of this value in a device with low resistance parasitics and excellent subthreshold swing is significant because this is the first time that these three features are shown in combination in an III-V MOSFETs. Fig. 7 shows typical transconductance characteristics at VDS = 0.5 V. The InAs QW MOSFET exhibits gm,max > 1.73 mS/μm at VDS = 0.5 V. This is a record transconductance for a III-V MOSFET of this gate length and VT and is mainly due to the well optimized Si δ-doping density that contributes to reduced access resistance and the high electron mobility associated with the InAs subchannel. Microwave performance was characterized from 0.5 GHz to 50 GHz. On-wafer open and short patterns were used to subtract pad parasitics from the measured device S-parameters. Fig. 8 plots h21, Ug and stability-factor (k) against frequency InAs MOSFET with Wg = 2 x 20 μm and Lg = 100 nm, at VGS = 0.7 and VDS = 0.8 V. We obtain a current-gain cut-off frequency fT = 245 GHz and a maximum oscillation frequency fmax = 355 GHz. These are record values among III-V MOSFETs of similar gate length. The device also exhibits fT = 238 GHz at VDS = 0.5 V. Small-signal parameter extraction from measured S-parameters gave good consistency between DC and RF transconductance. Conclusions: We have demonstrated Lg=100 nm recessed enhancement-mode quantum-well InAs MOSFETs with a composite Al2O3/InP gate stack. Lg = 100 nm devices exhibit outstanding logic characteristics, with S = 105 mV/dec, VT = 0.2 V, IOFF = 5 X 10 A/μm and gm,max > 1.73 mS/μm at VDS = 0.5 V. In addition, our devices show record fT = 245 GHz and fmax = 355 GHz. These results emerge from a well optimized inverted Si δ-doping, ALD high-k deposition and high mobility InAs channel design. Fig. 1: Cross-sectional schematic of QW device with 3 nm ALD Al2O3, 2 nm InP barrier and InAs composite channel. Fig. 2: TEM cross-section of fabricated device. Note well optimized recess with minimal Lside Fig. 3: 1D Poisson-Schrödinger simulations of channel electron density as a function of gate bias for different Si delta-doping concentrations. High δ-doping density limits charge modulation. Fig. 4: 1D Poisson-Schrödinger simulation of conduction band profile and electron wave-function at VGS=0 V. Reference: [1] R. Chau et al., IEEE T-Nano., p. 153 (2005). [2] Y. Sun et al., IEDM, p. 367 (2008). [3] M. Radosavljevic et al., IEDM, p.319 (2009) [4] T.-W. Kim et al., IEDM, p. 483 (2009). [5] D.-H. Kim et al., EDL, p. 830 (2008).